One of the key steps in the manufacture of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is formation of a gate electrode comprised of a conducing layer in which a gate length is typically one of the smallest dimensions in the device. To satisfy a constant demand for higher performance devices, the gate length is continually being reduced in each successive technology generation. For current technology, a gate length (LG) as small as 60 or 70 nm is required and LG will continue to shrink as sub-100 nm technology nodes are implemented in manufacturing. One shortcoming of state of the art lithography processes is that they are incapable of controllably printing features such as a gate in a photoresist layer with a LG smaller than about 100 nm. To overcome this limitation, many semiconductor fabs use a trimming process which laterally shrinks a photoresist feature such as a line with a plasma etch step.
A conventional MOSFET 1 is pictured in FIG. 1 and is typically fabricated by first forming isolation regions 3 such as shallow trench isolation (STI) regions comprised of an insulating material in a substrate 2. A gate dielectric layer 4 is formed on the substrate 2 and a gate layer which may be doped or undoped polysilicon is deposited on the gate dielectric layer 4. After the gate layer is patterned by conventional means to form a gate electrode 5 having a gate length d, the gate layer pattern is etch transferred through the gate dielectric layer 4. Ion implantation is used to form shallow source/drain regions 6 and deep source/drain regions 8. Sidewall spacers 7 are added adjacent to the gate electrode 5 and gate dielectric layer 4. Subsequently, a silicide layer (not shown) may be formed over the gate electrode 5 and deep source/drain regions 8 and contacts (not shown) may be formed to the silicide layer.
The gate pattern which defines the gate length d is initially formed by patternwise exposing a photoresist layer (not shown) on the gate layer and developing with an aqueous base to selectively remove exposed or unexposed portions of the photoresist layer depending upon the tone of the photoresist. A positive tone photoresist undergoes a reaction in exposed regions that renders them soluble in an aqueous base developer solution while unexposed portions of the photoresist film remain insoluble in the developer. In a negative tone photoresist, exposed regions are typically crosslinked to become insoluble in a developer while the unexposed portions are washed away in the developer.
A photoresist may be applied as a single layer or as the top layer of a bilayer system. A single layer photoresist is usually coated over an anti-reflective coating (ARC) that helps to control a subsequent imaging process. In bilayer applications, a pattern is formed in a thin photoresist layer and is etch transferred through a thicker underlayer that is used for its planarization and anti-reflective properties.
In some cases, a single layer or bilayer photoresist is selected in which the photoresist (imaging) layer is very opaque to the incident exposing radiation such that only a top portion near the surface absorbs energy and undergoes a chemical change. Top surface imaging techniques are frequently combined with a silylation process which forms O—Si bonds selectively in either the exposed or unexposed regions. For example, a silicon containing gas may react with a phenol group in the polymer component of a photoresist layer to yield O—Si bonds. A subsequent plasma etch that includes oxygen chemistry removes portions of the photoresist that are not protected by the O—Si bonds and thereby produces a pattern without the need of a developer solution.
The lithography process that is used to pattern the photoresist above the gate layer generally involves exposure tools which use wavelengths that are selected from a range of about 450 nm (near UV) to approximately 13 nm for extreme UV (EUV) exposures. High throughput projection electron beam tools that have the capability of imaging 50 to 70 nm resist features may be used in manufacturing in the near future. Even with the most advanced exposures tools, phase shifted masks, and other resolution enhancement techniques, the minimum feature size that can be reliably printed in a photoresist layer is not small enough to meet the demand for sub-100 nm gate lengths for most new devices. As a result, the industry has resorted to other methods that involve trimming the photoresist pattern such as an isotropic plasma etch process.
A plasma etching process employs the use of a photoresist mask to selectively allow an etchant to remove an underlying layer that has been exposed through openings in the mask pattern. In an anisotropic etch, the etchant only removes the underlying layer uncovered by the photoresist pattern. On the other hand, an isotropic etch involves removing exposed portions of the underlying layer along with some of the photoresist along the sidewalls of the openings in the pattern. Ideally, the photoresist layer is not distorted during the etch and should retain a majority of its thickness in order to avoid the formation of edge roughness and sidewall striations that may be transferred into the underlying layer. However, the polymers in photoresists developed for 193 nm or 157 nm lithography applications in new technologies do not contain aromatic groups which have an inherently high absorbance below about 240 nm. Therefore, the 193 nm and 157 nm photoresists based on acrylate and cyclic olefin based polymers are not as robust during a plasma etch process as their DUV (248 nm) or i-line (365 nm) predecessors which contain aromatic groups for high etch resistance.
Additionally, as the exposure wavelength shrinks to print smaller features in a photoresist layer, the thickness of the photoresist must also decrease to maintain a good focus and exposure latitude. Generally, the height of a photoresist line should not be more than about four times its width in order to prevent a phenomenon called line collapse. Therefore, etching sub-100 nm features using a thin 193 nm or 157 nm based photoresist mask of about 3000 Angstroms or less that has minimal etch resistance is problematic for single layer imaging schemes. Not only does the 193 nm or 157 nm photoresist have a lower etch resistance than DUV or i-line photoresists, but a thinner etch mask is used than in conventional DUV or i-line applications. At best, the amount of trimming or CD reduction is limited to about 10 nm or less for 193 nm or 157 nm photoresist layers which does not satisfy the need for large scale trimming of about 30 nm or more in many technologies.
One concept that has been practiced to overcome photoresist etching issues is to etch a pattern in a photoresist layer into an underlying hard mask that has a much better selectivity towards the gate layer than the photoresist. Once the pattern is transferred, the photoresist layer is stripped and the hard mask serves as the template for the etch transfer step to define the gate length in the gate layer. However, this method also has drawbacks including a poor profile control of the hard mask and damage to the gate layer and a silicon substrate when a hardmask such as silicon nitride is removed by phosphoric acid, for example.
In U.S. Pat. No. 6,500,755, a photoresist is patterned and trimmed on an optional cap layer on a dielectric layer. The pattern is etched into the cap layer and the photoresist is removed. A hard mask is deposited on the cap layer and is planarized to leave a portion of the cap layer exposed. The exposed cap layer and underlying dielectric layer are selectively removed by an etch to generate openings above a substrate.
In U.S. Pat. No. 6,482,726, a photoresist layer is patterned and trimmed above a second hard mask layer. The pattern is anisotropically etched through the second hard mask which may be SiO2. Once the photoresist layer is removed, a wet etch with H3PO4 isotropically transfers the pattern through an underlying first hard mask layer that is silicon nitride and laterally shrinks the first hard mask to a width less than that for the second hard mask. After the second hard mask is removed, the pattern is etched into a gate layer.
A multilayer anti-reflective coating (ARC) process is described in U.S. Pat. No. 6,548,423 in which a photoresist layer is patterned and trimmed above a second ARC which is silicon nitride or SiON. The pattern is anisotropically transferred through the second ARC and a first ARC which is CVD deposited carbon. The photoresist layer is stripped and the pattern is etched into an underlying gate layer using the ARCs as a combined hard mask.
An etching method is described in U.S. Pat. No. 6,492,068 in which a photoresist layer is patterned over a bottom ARC (BARC). The pattern is anisotropically etched through the BARC by a gas mixture including Ar, O2, Cl2, and HBr and is then transferred into an underlying gate layer with a Cl2, O2, and HBr plasma. The photoresist layer, BARC, and gate layer are trimmed simultaneously with an O2 and HBr plasma etch.
A bilayer trim etch process is found in U.S. Pat. No. 6,541,360 where a photoresist layer is patterned above an organic layer. The pattern is isotropically etched with a plasma through the bottom organic layer so that the organic layer has sloped sidewalls and a top that is smaller than its bottom. After the top layer is removed, the pattern is etched into a gate layer to give a gate length that is smaller than the width of the initial photoresist feature. However, a reproducible gate length may be difficult since it depends on trimming a sloped sidewall in the bottom layer with a high degree of control.
In U.S. Patent Application Publication US2002/0164543A1, a bilayer photolithography process is described in which an imaging layer is patterned over an underlayer and the pattern is transferred through the underlayer with an O2/HBr plasma process. The method prevents residue from forming on the sidewalls of the etched pattern that normally occurs with an O2/SO2 based plasma.
Thus, a new method of trimming a photoresist feature and transferring the resulting pattern into an underlying layer is needed that overcomes the limitations presented by a 157 nm or 193 nm single layer process, an isotropic etch, or a hard mask transfer step.